ECE
VLSI and digital design practice
Practice the skills VLSI and semiconductor roles test for. Write Verilog that is compiled and simulated against hidden testbenches, train your eye on predict-the-output questions, and work through the full RTL to GDSII flow in guided courses.
What you do here
Write-the-module Verilog problems
Each problem gives a spec and ports. Your RTL is compiled with Icarus Verilog and checked against hidden testbenches, including waveform problems where you match a timing diagram.
Predict-the-output questions
Short Verilog snippets covering X and Z propagation, signed and unsigned arithmetic, casez wildcards and blocking versus non-blocking assignment. The interview-question style, with explanations.
Courses for the whole flow
Step-by-step guides for logical synthesis, physical synthesis, physical design (place and route), static timing analysis, physical verification (DRC and LVS) and EM/IR drop analysis, each with the exact commands.
The tools around the flow
Tcl for VLSI scripting, Linux for the command line every EDA tool runs on, and GVim for editing netlists and reports quickly.
Topics covered
- Verilog HDL
- RTL design
- Combinational and sequential logic
- Finite state machines
- Testbenches and waveforms
- Logic synthesis
- Static timing analysis (STA)
- Setup and hold timing
- Physical design and place and route
- Floorplanning and power planning
- Clock tree synthesis
- DRC and LVS
- EM and IR drop
- Tcl scripting for EDA
Questions
- Do I need an EDA tool installed to practice Verilog here?
- No. Verilog runs in the browser: your code is compiled and simulated with Icarus Verilog on the server, and the result comes back with the failing test.
- Is this useful for VLSI interviews?
- Yes. Predict-the-output questions and write-the-module problems cover what front-end interviews ask, and the flow courses cover synthesis, STA and physical design for back-end roles.
- Is it free?
- Yes. Every problem and course is free, with no card required.